Polish pad with non-uniform groove depth to improve wafer polish rate uniformity

ABSTRACT

The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductorprocessing, and more specifically, to polishing methods and polishingpads for planarizing semiconductor materials in the fabrication ofsemiconductor devices.

[0003] 2. Background Information

[0004] Semiconductor devices manufactured today generally rely upon anelaborate system of semiconductor device layers, patterns, andinterconnects. The techniques for forming such various device layers,patterns, and interconnects are extremely sophisticated and are wellunderstood by practitioners in the art. During fabrication, however,these varying device layers, patterns, and interconnects often createnon-planar wafer topographies. Such non-planar wafer topographies causedifficulties when forming subsequent device layers, insulating layers,levels of interconnects, etc.

[0005] Some problems associated with non-planar topographies, forexample, are the interference and scattering of radiation by thenon-planar topography when performing photolithographic process steps.This makes it particularly difficult to print patterns with highresolution. Another problem with non-planar topographies is indepositing metal layers or lines. Uneven topographies, or step-heightsas they are often called, may cause thinning of the metal line/layer atpoints where the topography transitions from a high point to a lowpoint, and vice versa. Such thinning of the metal layers may cause opencircuits to be formed in the device or may cause the device to sufferreliability problems.

[0006] To combat these problems, various techniques have been developedin an attempt to planarize the topography of the wafer surface prior toperforming additional processing steps. One approach employs abrasivepolishing, for example chemical mechanical polishing (CMP), to removethe high points along the upper surface. According to this method, thewafer is placed on a table and is polished with a pad that has beencoated with an abrasive material (i.e. slurry). Both the wafer and thetable are rotated relative to each other to remove the high portions ofthe wafer topography. This abrasive polishing process continues untilthe upper surface of the wafer is largely planarized.

[0007] One problem with polishing to planarize the topography is thatthe polishing rates can become unstable and/or uneven across the surfaceof the wafer. For example, the profile of the topography in certainareas of the wafer may affect the polishing rate in that area. FIG. 1illustrates a simple example of the polishing rate profile of a wafer100. As is illustrated in FIG. 1, the polishing rate at the edges 110 ofwafer 100 is slower than the polishing rate toward the center 120 ofwafer 100 (i.e., edge slow). The difference in polish rates across thewafer may cause the topography of the wafer to be uneven afterpolishing. For example, the polishing rate profile of FIG. 1 may causethe wafer topography to have low points in the center of the wafer andhigh points around the edges of the wafer, rather than a flat or planarsurface as is desired.

[0008] It is desired to have an even polish rate profile across thewafer surface in order to improve the planarity of the polishingprocess. As illustrated in FIG. 1, an ideal polish rate profile isillustrated in FIG. 1 by dashed line 150. In order to arrive at theideal polish rate profile 150, what is needed is method to increase thepolish rate at the edges of the wafer 110, and decrease the polish rateat the center of the wafer 120. The ideal polish rate profile 150 willimprove the surface planarity of the polishing process.

[0009]FIGS. 2 and 3 also illustrate examples wherein the polishing ratesare uneven/unstable across the surface of a wafer. FIG. 2, illustratesthe opposite effect of FIG. 1, wherein the polishing rate at the edges210 of wafer 200 is faster than the polishing rate toward the center 220of wafer 200 (i.e., center slow). Thus in FIG. 2, what is needed is amethod to decrease the polish rate at the edges of the wafer 210, andincrease the polish rate at the center of the wafer 220, in order toobtain the ideal polish rate profile 250. FIG. 3, illustrates a worstcase scenario wherein the polishing rate varies randomly across theentire wafer surface. Thus in FIG. 3, what is needed is a method todecrease the polish rate in the areas of the wafer 300 where the polishrate is high, and increase the polish rate in the areas of the wafer 300where the polish rate is low, in order to obtain the ideal polish rateprofile 350.

[0010] Thus, what is needed is a method to increase the polish rate inthe areas of a semiconductor wafer that the polish rate is low and/ordecrease the polish rate in the areas of a semiconductor wafer that thepolish rate is high in order to improve the planarization process of thesemiconductor wafer.

SUMMARY OF THE INVENTION

[0011] The present invention describes a method for creating adifferential polish rate across a semiconductor wafer. One embodiment ofthe present invention determines the profile of the semiconductor waferby locating the high points and low points of the wafer profile. Agrooved polish pad is provided and then the groove depth of the polishpad is adjusted by increasing the groove depth in the areas of thepolish pad that correspond to the high points of said wafer profile. Thesemiconductor wafer is then polished with the polish pad.

[0012] Additional features and benefits of the present invention willbecome apparent from the detailed description, figures, and claims setforth below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention is illustrated by way of example and notlimitation in the accompanying figures in which:

[0014]FIG. 1 illustrates an edge slow polish rate profile of asemiconductor wafer.

[0015]FIG. 2 illustrates a center slow polish rate profile of asemiconductor wafer.

[0016]FIG. 3 illustrates a random polish rate profile of a semiconductorwafer.

[0017]FIG. 4a illustrates a cross-sectional view of a polish pad havingv-shaped grooves.

[0018]FIG. 4b illustrates a cross-sectional view of a polish pad havingu-shaped grooves.

[0019]FIG. 4c illustrates a cross-sectional view of a polish pad havingone-sided triangle grooves.

[0020]FIG. 5a illustrates a cross-sectional view of a polish pad havingv-shaped grooves according to one embodiment of the present inventionand the polish rate profile of FIG. 1.

[0021]FIG. 5b illustrates a cross-sectional view of a polish pad havingu-shaped grooves according to another embodiment of the presentinvention and the polish rate profile of FIG. 1.

[0022]FIG. 6 illustrates a cross-sectional view of a polish pad havingu-shaped grooves according to still another embodiment of the presentinvention and the polish rate profile of FIG. 2.

[0023]FIG. 7 illustrates a cross-sectional view of a polish pad havingu-shaped grooves according to yet another embodiment of the presentinvention and the polish rate profile of FIG. 3.

DETAILED DESCRIPTION

[0024] A(n) Polish Pad With Non-Uniform Groove Depth To Improve WaferPolish Rate Uniformity is disclosed. In the following description,numerous specific details are set forth such as specific materials,patterns, dimensions, etc. in order to provide a thorough understandingof the present invention. It will be obvious, however, to one skilled inthe art that these specific details need not be employed to practice thepresent invention. In other instances, well known materials or methodshave not been described in detail in order to avoid unnecessarilyobscuring the present invention.

[0025] The present invention describes a method for improving thesurface planarity during the fabrication of semiconductor device layers.The multilayered structure of current semiconductor devices often leadsto non-planar surfaces that can cause problems during the fabrication ofsubsequent device layers. One method developed to help solve the problemof non-planar wafer topographies is the use of chemical mechanicalpolishing (CMP) to planarize the wafer surface.

[0026] There are many factors that play a part in the planarizationprocess. For chemical mechanical polishing, some of these factorsinclude: the rotation rates of the polishing pad and wafer, the wafertopography or profile (i.e. the high points and low points on the wafersurface), the pressure with which the pad and wafer are put in contact,the material making up the polish pad, the slurry being used, thematerial being polished/planarized/removed, etc. All of these factorsare important to the planarization process, however, even if all ofthese factors are optimized some planarization problems may still exist.

[0027] The present invention may be used singly or in combination withany of the above mentioned factors and optimization parameters toimprove the planarization process. One embodiment of the presentinvention determines the profile or topography of the wafer. In otherwords, it is determined where the high points and low points are on thewafer surface. It should be obvious to one with ordinary skill in theart that well know methods for determining wafer topography may be usedand are therefore not discussed in detail herein.

[0028] Typically, a polish pad will contain grooves such as thoseillustrated in FIGS. 4a-c. FIG. 4a illustrates a polish pad havingv-shape grooves therein. FIG. 4b illustrates a polish pad having u-shapegrooves therein. FIG. 4c illustrates a polish pad having single-sidedtriangle grooves therein. Although, FIGS. 4a-c illustrate only a singleshape of groove per polish pad, it should be noted that different grooveshapes and/or a combination of groove shapes may be used on a polishpad.

[0029] Generally, the grooves are cut into the polish pad duringmanufacture of the polish pad and are usually uniformly spaced acrossthe diameter of the polish pad. Additionally, the groove depth andgroove width are uniform across the polish pad surface. However, suchuniform groove density, groove width, and groove depth may causenon-uniform polish rates across the wafer surface such as thoseillustrated in FIGS. 1-3, edge slow, center slow, and random,respectively.

[0030] The present invention improves the planarization process byadjusting and/or changing the grooves which are in the polishing pad.Groove shape, groove depth, groove width, and groove density all play apart in the planarization process. Changing the groove shape, groovedepth, groove width, and/or groove density, either singly or incombination, can affect the polishing rate of the wafer. As such,changing the groove shape, groove depth, groove width, and/or groovedensity, either singly or in combination, also affects the polish rateprofile of the wafer.

[0031] By changing the grooves in the areas of the polish pad thatcorrespond to the areas of the wafer where the high points and lowpoints of the wafer topography and/or the areas where the polish rateprofile is either high or low, the polish rate may be stabilized.Stabilizing the polish rate will in turn improve planarization. Byincreasing the groove depth, width, and/or density the polish rate isincreased which will more effectively remove the high points in thewafer topography and/or stabilize the polish rate in areas of the waferwhere the polish rate would have been too low. For example in FIG. 1that illustrates edge slow, the groove depth, width, and/or densitywould be increased in the areas of the polish pad that correspond to theedges of the semiconductor wafer in order to increase the polish rate sothat the desirable polish profile 150 may be achieved.

[0032] By decreasing the groove depth, width, and/or density the polishrate is decreased which will remove less of the topography near the lowpoints and/or stabilize the polish rate in areas of the wafer where thepolish rate would have been too high and otherwise would have removedtoo much of the topography. For example, in FIG. 2 that illustratescenter slow, the groove depth, width, and/or density would be decreasedin the areas of the polish pad that correspond to the center of thesemiconductor wafer in order to decrease the polish rate at the centerof the wafer so that the desirable polish profile 250 may be achieved.Similar adjustments may be made in FIG. 3 that illustrates a randomwafer profile in order to achieve the desirable polish rate profile 350.

[0033] It should be noted and it will be obvious to one with ordinaryskill in the art given this description that the grooves may be changedin any number of combinations. For example, in FIG. 1 that illustratesedge slow, the groove depth, width, and/or density may be increased atthe edges of the wafer and may be decreased at the center of the wafer.Depending upon the result desired by the user, just the groove depth, orjust the groove width, or just the groove density may be increased ordecreased in some areas. The user may also determine that it would bemore beneficial to adjust groove depth and groove width, or groove depthand groove density, or groove width and groove density, or all three:groove depth, width, and density in some areas to obtain the desiredresult. Thus, the grooves may be adjusted in many various combinationsin order to achieve the optimum polish rate profile desired by aparticular user.

[0034]FIG. 5a illustrates a cross-sectional view of a polish pad havingv-shaped grooves according to one embodiment of the present inventionand the polish rate profile of FIG. 1. In order to achieve the desiredpolish rate profile 150 the groove width and groove depth of the groovesin the center of the polish pad of FIG. 5a are increased in order toincrease the polish rate at the center of the wafer. FIG. 5b illustratesa cross-sectional view of a polish pad having u-shaped grooves accordingto another embodiment of the present invention and the polish rateprofile of FIG. 1. Similar to FIG. 5a, the grooves of the polish pad inFIG. 5b increase in depth and density in order to increase the polishrate at the center of the wafer. The polish pads of FIGS. 5a and 5 bcorrespond to a wafer profile wherein the wafer has low points at theedge of the wafer and high points at the center of the wafer. Thus,where the wafer profile has high points in the center of the wafer andthe polish rate would ordinarily be slow the present invention increasesthe groove depth, width, and/or density in order to increase the polishrate and remove the high points of the topography to achieve the desiredwafer profile 150.

[0035]FIG. 6 illustrates a cross-sectional view of a polish pad havingu-shaped grooves according to still another embodiment of the presentinvention and the polish rate profile of FIG. 2. The polish pad of FIG.6 corresponds to a wafer profile wherein the wafer has high points atthe edge of the wafer and low points at the center of the wafer. Asillustrated in FIG. 6 the depth and width of the grooves at the edgesare increased in order to increase the polish rate at the edges of thewafer. Also, as illustrated in FIG. 6 the depth and width of the groovesat the center of the polish pad are decreased in order to reduce (ordecrease) the polish rate at the center of the wafer. Thus, the polishpad of FIG. 6 may be used to increase the polish rate at the edge of thewafer and decrease the polish rate in the center of the wafer in orderto achieve the desired polish rate profile 250 illustrated in FIG. 2.

[0036]FIG. 7 illustrates a cross-sectional view of a polish pad havingu-shaped grooves according to yet another embodiment of the presentinvention and the polish rate profile of FIG. 3. The polish pad of FIG.7 corresponds to a wafer profile wherein the wafer has random highpoints and low points. As illustrated in FIG. 7 the depth, width, anddensity of the grooves are increased in the areas of the polish padcorresponding to high points of the wafer profile in FIG. 3. Also, asillustrated in FIG. 7 the depth, width, and density of the grooves aredecreased in the areas of the polish pad corresponding to low points ofthe wafer profile in FIG. 3. Thus, the polish pad of FIG. 7 may be usedto increase the polish rate in areas of the wafer wherein the highpoints would otherwise cause the polish rate to be low and decrease thepolish rate in areas of the wafer wherein the low points would otherwisecause the polish rate to be too high in order to achieve the desiredpolish rate profile 350 illustrated in FIG. 3.

[0037] It should be noted that the grooves of the polish pad should beadjusted while keeping in mind the parameters of the particular polishpad so not to degrade the usefulness of the polish pad. For example, thedepth of the grooves should not be increase to the point where thepolish pad becomes weak or brittle. As another example, the width of thegrooves should not be increased to be so large as not to be effective orcover too large an area on the polish pad. Likewise, the density of thegrooves should not be increased beyond the point where the portions ofthe polish pad that separate the grooves are too thin or brittle and maybreak.

[0038] In one embodiment of the present invention the groove depth isadjusted within the range of approximately 1-90% of the pad thickness.In another embodiment of the present invention the groove width isadjusted within the range of approximately 1-100 mils. In yet anotherembodiment of the present invention the groove density is adjustedwithin the range of approximately 2-50 grooves/inch. It will be obviousto one with ordinary skill in the art that such parameters may bedependent upon the strength, durability, surface area, pad thickness,material, and etc. that make up the polish pad.

[0039] It should be noted that deeper and/or wider and/or more densegrooves improve slurry transport and distributes more slurry to theareas where a higher polish rate is desired. It should also be notedthat wider grooves and/or more dense grooves increase the pressure inthe areas where a higher polish rate is desired. By changing the groovedepth, width, and/or density the present invention distributes moreslurry and/or increases the pressure of the polish pad in the areaswhere a higher polishing rate is desired in order to achieve the desiredpolish profiles, for example, polish profiles 150, 25Q, and 350illustrated in FIGS. 1, 2, and 3, respectively.

[0040] Thus, Polish Pad With Non-Uniform Groove Depth To Improve WaferPolish Rate Uniformity has been described. Although specificembodiments, including specific equipment, patterns, methods, andmaterials have been described, various modifications to the disclosedembodiments will be apparent to one of ordinary skill in the art uponreading this disclosure. Therefore, it is to be understood that suchembodiments are merely illustrative of and not restrictive on the broadinvention and that this invention is not limited to the specificembodiments shown and described.

What is claimed is:
 1. A method for creating a differential polish rateacross a wafer comprising: determining the profile of said wafer, saidwafer profile having high points and low points; providing a polish padhaving a plurality of grooves; adjusting the groove depth of said polishpad, wherein said groove depth is increased in the areas of said polishpad that correspond to the high points of said wafer profile; andpolishing said wafer with said polish pad.
 2. The method as described inclaim 2 further comprising the step of: adjusting the groove width ofsaid polish pad, wherein said groove width is increased in the areas ofsaid polish pad that correspond to the high points of said waferprofile.
 3. The method as described in claim 2 further comprising thestep of: adjusting the groove density of said polish pad, wherein saidgroove density is increased in the areas of said polish pad thatcorrespond to the high points of said wafer profile.
 4. The method asdescribed in claim 1 wherein said plurality of grooves have a shapeconsisting of: a v-shape, a u-shape, a one-sided-triangle, or acombination thereof.
 5. The method as described in claim 1 wherein saidgroove depth is adjusted within the range of approximately 1-90% of thepad thickness.
 6. The method as described in claim 2 wherein said groovewidth is adjusted within the range of approximately 1-100 mils.
 7. Themethod as described in claim 3 wherein said groove density is adjustedwithin the range of approximately 2-50 grooves/inch.
 8. A method forcreating a differential polish rate across a wafer comprising:determining the profile of said wafer, said wafer profile having highpoints and low points; providing a polish pad having a plurality ofgrooves; adjusting the groove width of said polish pad, wherein saidgroove width is increased in the areas of said polish pad thatcorrespond to the high points of said wafer profile; and polishing saidwafer with said polish pad.
 9. The method as described in claim 8further comprising the step of: adjusting the groove depth of saidpolish pad, wherein said groove depth is increased in the areas of saidpolish pad that correspond to the high points of said wafer profile. 10.The method as described in claim 8 further comprising the step of:adjusting the groove density of said polish pad, wherein said groovedensity is increased in the areas of said polish pad that correspond tothe high points of said wafer profile.
 11. The method as described inclaim 8 wherein said plurality of grooves have a shape consisting of: av-shape, a u-shape, a one-sided-triangle, or a combination thereof. 12.The method as described in claim 8 wherein said groove width is adjustedwithin the range of approximately 1-90% of the pad thickness.
 13. Themethod as described in claim 9 wherein said groove depth is adjustedwithin the range of approximately 0.01-50 mils.
 14. The method asdescribed in claim 10 wherein said groove density is adjusted within therange of approximately 2-50 grooves/inch.
 15. A method for creating adifferential polish rate across a wafer comprising: determining theprofile of said wafer, said wafer profile having high points and lowpoints; providing a polish pad having a plurality of grooves; increasingthe polish rate of said polish pad in the areas of said polish pad thatcorrespond to the high points of said wafer profile; and polishing saidwafer with said polish pad.
 16. The method as described in claim 15wherein said step of increasing the polish rate comprises increasing thegroove depth of said grooves in the areas of said polish pad thatcorrespond to the high points of said wafer profile.
 17. The method asdescribed in claim 15 wherein said step of increasing the polish ratecomprises increasing the groove width of said grooves in the areas ofsaid polish pad that correspond to the high points of said waferprofile.
 18. The method as described in claim 15 wherein said step ofincreasing the polish rate comprises increasing the groove density ofsaid grooves in the areas of said polish pad that correspond to the highpoints of said wafer profile.
 19. The method as described in claim 15wherein said plurality of grooves have a shape consisting of: a v-shape,a u-shape, a one-sided-triangle, or a combination thereof.
 20. Themethod as described in claim 16 wherein said groove depth is adjustedwithin the range of approximately 1-90% of the pad thickness.
 21. Themethod as described in claim 17 wherein said groove width is adjustedwithin the range of approximately 1-100 mils.
 22. The method asdescribed in claim 18 wherein said groove density is adjusted within therange of approximately 2-50 grooves/inch.
 23. The method of claim 15further comprising the step of: decreasing the polish rate of saidpolish pad in the areas of said polish pad that correspond to the lowpoints of said wafer profile.
 24. The method as described in claim 23wherein said step of decreasing the polish rate comprises decreasing thegroove depth of said grooves in the areas of said polish pad thatcorrespond to the low points of said wafer profile.
 25. The method asdescribed in claim 23 wherein said step of decreasing the polish ratecomprises decreasing the groove width of said grooves in the areas ofsaid polish pad that correspond to the low points of said wafer profile.26. The method as described in claim 23 wherein said step of decreasingthe polish rate comprises decreasing the groove density of said groovesin the areas of said polish pad that correspond to the low points ofsaid wafer profile.
 27. A polish pad for creating a differential polishrate across a wafer comprising: said polish pad having a plurality ofgrooves; said grooves having an increased depth in areas that correspondto high points on the surface of said wafer; and said grooves having adecreased depth in areas that correspond to low points on the surface ofsaid wafer.
 28. The polish pad as described in claim 27 furthercomprising: said grooves having an increased width in areas thatcorrespond to high points on the surface of said wafer; and said grooveshaving a decreased width in areas that correspond to low points on thesurface of said wafer.
 29. The polish pad as described in claim 27further comprising: said grooves having an increased density in areasthat correspond to high points on the surface of said wafer; and saidgrooves having a decreased density in areas that correspond to lowpoints on the surface of said wafer.
 30. The polish pad as described inclaim 27 wherein said plurality of grooves have a shape consisting of: av-shape, a u-shape, a one-sided-triangle, or a combination thereof. 31.The polish pad as described in claim 27 wherein said groove depth isadjusted within the range of approximately 1-90% of the pad thickness.32. The polish pad as described in claim 28 wherein said groove width isadjusted within the range of approximately 1-100 mils.
 33. The polishpad as described in claim 29 wherein said groove density is adjustedwithin the range of approximately 2-50 grooves/inch.
 34. A polish padfor creating a differential polish rate across a wafer comprising: saidpolish pad having a plurality of grooves; said grooves having anincreased width in areas that correspond to high points on the surfaceof said wafer; and said grooves having a decreased width in areas thatcorrespond to low points on the surface of said wafer.
 35. The polishpad as described in claim 34 further comprising: said grooves having anincreased depth in areas that correspond to high points on the surfaceof said wafer; and said grooves having a decreased depth in areas thatcorrespond to low points on the surface of said wafer.
 36. The polishpad as described in claim 34 further comprising: said grooves having anincreased density in areas that correspond to high points on the surfaceof said wafer; and said grooves having a decreased density in areas thatcorrespond to low points on the surface of said wafer.
 37. The polishpad as described in claim 34 wherein said plurality of grooves have ashape consisting of: a v-shape, a u-shape, a one-sided-triangle, or acombination thereof.
 38. The polish pad as described in claim 34 whereinsaid groove width is adjusted within the range of approximately 1-90% ofthe pad thickness.
 39. The polish pad as described in claim 35 whereinsaid groove depth is adjusted within the range of approximately 0.01-50mils.
 40. The polish pad as described in claim 36 wherein said groovedensity is adjusted within the range of approximately 2-50 grooves/inch.41. A polish pad for creating a differential polish rate across a wafercomprising: said polish pad having a plurality of grooves; said grooveshaving an increased density in areas that correspond to high points onthe surface of said wafer; and said grooves having a decreased densityin areas that correspond to low points on the surface of said wafer. 42.The polish pad as described in claim 41 further comprising: said grooveshaving an increased width in areas that correspond to high points on thesurface of said wafer; and said grooves having a decreased width inareas that correspond to low points on the surface of said wafer. 43.The polish pad as described in claim 41 further comprising: said grooveshaving an increased depth in areas that correspond to high points on thesurface of said wafer; and said grooves having a decreased depth inareas that correspond to low points on the surface of said wafer. 44.The polish pad as described in claim 41 wherein said plurality ofgrooves have a shape consisting of: a v-shape, a u-shape, aone-sided-triangle, or a combination thereof.
 45. The polish pad asdescribed in claim 41 wherein said groove density is adjusted within therange of approximately 2-50 grooves/inch.
 46. The polish pad asdescribed in claim 42 wherein said groove width is adjusted within therange of approximately 1-100 mils.
 47. The polish pad as described inclaim 43 wherein said groove depth is adjusted within the range ofapproximately 1-90% of the pad thickness.
 48. A polish pad comprising: aplurality of grooves, said plurality of grooves having varying groovedensities.
 49. The polish pad as described in claim 48 wherein saidgroove density is adjusted within the range of approximately 2-50grooves/inch.
 50. A polish pad comprising: a plurality of grooves, saidplurality of grooves having varying groove depths.
 51. The polish pad asdescribed in claim 50 wherein said groove depth is adjusted within therange of approximately 1-90% of the pad thickness.
 52. A polish padcomprising: a plurality of grooves, said plurality of grooves havingvarying groove widths.
 53. The polish pad as described in claim 52wherein said groove width is adjusted within the range of approximately1-100 mils.